This invention relates to the field of solid state photo-sensors and imagers referred to as Active Pixel Sensors (APS) that have active circuit elements associated with each pixel, and more specifically to Solid State Imagers that employ correlated double sampling (CDS).
APS are solid state imagers wherein each pixel contains the typical solid state pixel elements including a photo-sensing means, reset means, a charge to voltage conversion means, and additionally all or part of an amplifier. The photocharge collected within the pixel is converted to a corresponding voltage or current within the pixel as discussed in prior art documents such as xe2x80x9cActive Pixel Sensors: Are CCD""s Dinosaurs?xe2x80x9d, SPIE Vol. 1900-08-8194-1133 July 1993, by Eric Fossum. APS devices have been operated in a manner where each line or row of the imager is selected and then read out using a column select signal as discussed by E. Fossum in xe2x80x9cActive Pixel Sensors: Are CCD""s Dinosaurs?xe2x80x9d, SPIE Vol. 1900-08-8194-1133 July 1993 and by R. H. Nixon, S. E. Kemeny, C. O. Staller, and E. R. Fossum, in xe2x80x9c128xc3x97128 CMOS Photodiode-type Active Pixel Sensor with On-chip Timing, Control and Signal Chain Electronicsxe2x80x9d. Proceedings of the SPIE vol. 2415, Charge-Coupled Devices and Solid-State Optical Sensors V, paper 34 (1995). The selection of rows and columns within an Active Pixel Sensor is analogous to the selection of words and bits in memory devices. Here, the selection of an entire row would be analogous to selecting a word and the reading out of one of the columns of the Active Pixel Sensor would be analogous to selecting or enabling a single bit line within that word. Conventional prior art devices teach architectures employing 3 transistor designs, where the 3 transistors are typically Row Select, Reset, and Source Follower Amplifier transistors. While this architecture provides the advantages of yielding APS devices having a reasonably high pixel fill factor, it does not provide the capability to easily perform CDS. CDS is a technique that provides referencing of the signal level of a pixel to the reset level of that pixel. In order to perform CDS, the pixel must first be reset and the reset level of the pixel readout prior to integration or photocharge collection within that pixel. Next incident light results in photoelectrons being generated within the photodetector resulting in a signal charge that is accumulated within the pixel, which can then be read out. This results because the photodetector is also a charge to voltage conversion means. When the photodetector is reset, the charge in the photodetector is removed via the pixel supply voltage and cannot be recovered. This technique reduces the temporal noise of the sensor, providing a higher signal to noise ratio and better image quality.
Prior art devices that perform CDS employing 3 transistor based pixels, typically first read out and store an image frame comprising a reset level for each pixel on the sensor. Next the signal frame is captured and read out. The reset level frame stored in memory must then be subtracted from the signal frame at each pixel to provide a pixel signal level that is referenced to the pixel reset level prior to integration. Prior art designs using 4 transistor pixels have been devised that enable CDS without the need to capture and store a separate reset frame, but the 4 transistor cells have the shortcoming of having a lower fill factor and lower sensitivity than 3 transistor pixels.
In addition, prior art 4T pixel designs can produce an artifact called image lag where all of the photoelectrons cannot be read out in a single frame, and appear as a ghost or residual image in the next frame. The signal swing in 4T pixels is also limited and less than that of 3T pixel designs due to the restriction of prevention of charge sharing between the photodetector and floating diffusion during readout.
Typical prior art APS pixels are shown in FIGS. 1a and 1b. The pixel in FIG. 1a is a prior art 3 transistor pixel that comprises: a photodetector (PDET), that can be either a photodiode (PD) or a photogate (PG); reset transistor with a reset gate (RG); row select transistor with a row select gate, (RSG); and a source follower input signal transistor (SIG). The pixel in FIG. 1b is a prior art 4 transistor pixel and comprises a photodetector (PDET); that can be either a photodiode (PD) or photogate (PG); a transfer gate (TG); a floating diffusion (FD); reset transistor with a reset gate (RG); row select transistor with a row select gate, (RSG); and source follower input signal transistor (SIG). As stated above it is difficult to perform CDS using the prior art 3 transistor pixel architecture. The photodetector is also used as the charge to voltage conversion node within prior art 3 transistor pixel . In order to obtain the pixel reset level prior to signal integration, the reset level of the entire frame must be read out and stored in memory prior to commencing integration. If one were to reset the photodetector prior to integration, read the reset level, then integrate and read the signal level, that entire sequence would have to be done one row at a time. Hence if the desired integration time were 30 msec., each row would have to be independently and separately integrated for 30 msec. If there were 1000 rows in the image sensor, a frame with 30 msec. integration time would take 30 seconds to capture. In addition, any changes in illumination of the scene or motion of objects in the scene within the 30 seconds would produce an undesirable image artifact in the form of image tear, blur and shading.
In the 4 transistor pixel, since the photodetector is separated from the charge to voltage conversion node (floating diffusion, FD) by an extra transistor, the floating diffusion can be reset, and the reset level of the floating diffusion can be read immediately prior to transferring the signal charge onto the floating diffusion. Thus CDS can be accomplished without separate and non-overlapping integration periods for each and every row. However the area required to implement the 4th transistor reduces the fill factor of the pixel compared to the 3 transistor pixel.
It should be readily apparent that there remains a need within the art to provide an alternate pixel architecture that has high fill factor, no lag, large image signal swing, and the capability to perform CDS without the need to capture and store entire frames of image data in order to be able to subtract a separate reset frame from each signal level frame, or to have separate and non-overlapping integration periods for each row of the sensor.
The present invention provides a means to perform Correlated Double Sampling, (CDS), within a 3 transistor, Active Pixel Architecture. This is done by AC coupling the photodetector signal to the input of the source follower in the pixel, and providing a means to clamp the input of source follower to a reference signal.
The present invention addresses the needs within the prior art by providing an Active Pixel Sensor having a plurality of pixels with the pixel designed having a photodetector operatively connected to a first electrical node on a signal coupling capacitor with the opposite side of the signal coupling capacitor connected to a second electrical node and a reset configuration that applies predetermined potentials to the first and second electrical nodes upon reset. The preferred embodiment applies a voltage supply to these nodes upon reset and allows the voltage on the first node connected to the photodetector to accumulate charge during the time period following reset. The second electrical node is allowed to float following reset so the accumulated charge is saved on the capacitor with reference to the predetermined potentials. An amplifier is operatively connected to the second electrical node to sense and read out the signal from the second electrical node. In the preferred embodiment, a reset transistor having two sources connected to each the first and second electrical nodes is employed, however, two reset transistors can also perform the same function. The signal capacitor is preferably formed by overlapping a portion of the photodetector with an extension of the amplifier gate electrode.
The present invention provides true Correlated Double Sampling (CDS) using only 3 transistors resulting in a higher fill factor. The advantage gained is high fill factor, lower temporal noise, lag free, and large signal swing, and voltage scaling in deep sub-xcexc CMOS. No disadvantages foreseen.